Chips of semiconductor light emitting devices (hereinafter referred to as "LED chips") that generate blue to yellow light of high luminance are conventionally manufactured in the following manner. As shown in FIG. 3, there are sequentially formed, through epitaxial growth onto a sapphire substrate 21, an n-type layer (cladding layer) 23 of e.g. n-type GaN, an active layer (light emitting layer) 24 of e.g. InGaN based compound semiconductor (wherein the ratio of In and Ga may be varied as it similarly applies hereinafter) which is a material whose band gap energy is smaller than that of the cladding layer and which determines the light emitting wavelength, and a p-type layer (cladding layer) 25 of p-type GaN. A p-side electrode 28 is formed onto a surface of the laminated semiconductor layers with a current diffusion layer 27 interposed between, and a part of the laminated semiconductor layers is etched so that an n-side electrode 29 is formed on the exposed surface of the n-type layer 23. A protecting film 30 of e.g. SiO.sub.2 is further provided on the surface such that the electrodes 28, 29 are exposed therefrom, and dicing is performed to obtain a dicing groove 31 having a depth of approximately several tens of .mu.m. After grinding a rear surface of the substrate 21 for thinning the wafer from approximately 350 .mu.m to assume a thickness of approximately 100 .mu.m, a scribe line 21a is formed from the rear surface of the substrate 21 at boundary line S of the chips by using a diamond cutter or the like, and by applying force to the portion of the scribe line 21a, breaking is performed to divide the wafer into individual chips.
Since a sapphire substrate is extremely hard, the depth of the scribe line 21a will be a shallow cut of not more than several .mu.m. It should be noted that an AlGaN based (wherein the ratio of Al and Ga may be varied as it similarly applies hereinafter) compound semiconductor layer may be used on the side of the active layer 23 since n-type layer 23 and p-type layer 25 function to improve confinement effect of carriers. Further, when performing etching of the above-described semiconductor layers to be laminated, portions to be broken are simultaneously etched at the boundary lines S of individual chip to expose the n-type layer 23 whereby easy breaking is made possible.
In case dividing is performed through dicing after a protection film is provided on the surface side of the semiconductor layers in the above-described manner, the protection film 30 may cause chipping at the time of performing dicing such that cracks directed to various directions may be formed on the protection layer 30 by an edge of a dicer so that the yield factor is degraded. In order to solve this problem, it is generally performed that dicing is performed after removing the protection film 30 of portions to be diced, as shown in the sectional view and the plan view of FIG. 3 and FIG. 4, respectively. In this case, width A for removing the protection layer is required to be approximately 60 .mu.m in view of the fact that width W of the dicing groove 31 is approximately 20 .mu. m, that distance B between the dicing groove 31 and the protection film 30 is at least required to be approximately 15 .mu.m in view of reliability, and that a positional shift of the dicing groove 31 be approximately 5 .mu.m.
As explained above, in case dicing is performed after forming a protection film on a surface side of the semiconductor layers, it is presented a drawback that the protection film be damaged to be inferior in reliability and that the yield factor be degraded in case dicing is performed without removing the protection film. On the other hand, in case removal of the protection film at portions to be diced is preliminarily performed, it is required to secure two margins, one for the pattern shift at the time of etching the protection film and the positional shift at the time of dicing, so that intervals between chips need to be kept wider. This will result in a fewer number of chips to be obtained from a wafer though the sizes of the wafers may be identical, and will cause a drawback in that the costs become higher.